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Speech Recognition is the process in which words of a speaker will be automatically recognized as text or some predefined instruction or code based upon the information included in individual speech waves. A robust speech-recognition system combines accuracy of speech identification with the ability to filter out noise and adapt to other acoustic conditions, such as the speaker’s speech rate and accent. Speech-recognition technology is nowadays embedded in voice-activated routing systems at customer call centers, voice dialing on mobile phones, transcription (voice to text), managing stuff (creating voice commands),web search, GPS navigation, vending machines, smart homes and many other everyday applications. ASR System can be: Speaker dependent, Speaker independent, Isolated Word, Limited Vocabulary, Continuous Speech, Unlimited Vocabulary. Products Used include: ■ MATLAB© ■ Data Acquisition Toolbox™ ■ Signal Processing Toolbox™ ■ Statistics Toolbox™ ■ ASR System Overview: The basic workflow is demonstrated considering an isolated; speaker dependent digit recognition system. It comprise of three steps: ■ Speech acquisition For training, speech is acquired from a microphone and brought into the development environment for offline analysis. For testing, speech is continuously streamed into the environment for online processing. Data Acquisition Toolbox™ is used to set up continuous acquisition of the speech signal and for simultaneous extraction of frames of data for processing. Speech processing includes: Pre-emphasis (Flatten the magnitude spectrum), Frame Blocking (Speech is short term predictable), Windowing (Remove the discontinuities at the beginning and the end of each frame). ■ Speech analysis Developing a Speech-Detection Algorithm : The speech-detection algorithm is developed by processing the prerecorded speech frame by frame within a simple loop. Developing the Acoustic Model : A good acoustic model should be derived from speech characteristics that will enable the system to distinguish between the different words in the dictionary. ■ User interface development After developing the isolated digit recognition system in an offline environment with pre-recorded speech, we migrate the system to operate on streaming speech from a microphone input. We use MATLAB GUIDE tools to create an interface that displays the time domain plot of each detected word as well as the classified digit (Figure1). Speech Recognition Author - Sushant shama (Research Associate at Sillicon Mentor)

Hardware description language (HDL) plays a vital role in very large scale integration (VLSI). HDLs looks much like a programming language C. HDL is textual description of an electronic circuit or electronic chip. In other words HDL is used to describe hardware in terms of expressions and statements, control structures. HDL is concurrent (all parts work at the same time)whereas traditional software is sequential. HDL is real time sensitive unlike software. HDL also allows for the compilation of an HDL program into a lower level specification of physical electronic components, such as the set of masks used to create an integrated circuit. HDL has ability to describe and simulate at behavioural, structural and mixed level. From above description we can say that HDL form an integral part of electronic design automation system, specially for complex circuits such as microprocessor. Now we will know more about HDLs. There are two types of HDL which is supported by IEEE. They are VHDL ( Very high speed integrated circuit HDL) and Verilog HDL. These language are used in electronic devices that do not share computer’s basic architecture. For high level modeling VHDL is better while Verilog is better for gate level modeling and switch level modeling. VHDL is not case sensitive while Verilog is case sensitive. Verilog is similar to C or PASCAL language while VHDL is similar to ADA programming language in syntax. VHDL is more complex then verilog. VHDL has the advantage of having a lot of constructs that aid in high level modeling. Verilog is easy to understand and easy to design. VHDL is different from Verilog in terms of signal assignment, interface declaration, in RTL assignment. Verilog is much better then VHDL below the RTL level. VHDL and Verilog is equivalent for RTL modeling. But the bottom line is that we should know both. Verilog-HDL Tags : HDL, Verilog , VHDL , RTL , FPGA Vs ASIC , Verilog Training Author - Trisha Jain (Intern at Silicon Mentor)

Some days ago I was searching for some good content on current market status of semiconductor industry. There I found something interesting about the semiconductor/VLSI companies recruitment policies, most of them are focused on the individual technical skill not on the education background. It is true in some of the cases like if you search job advertisement of some of the SMEs they usually gives preference to IIT/NITs students whereas the companies like Silab Tech , Spontey, Smart play, Cadence etc. they gives chance to work other Indian university students also. Semiconductors Therefore to get a entry level job in a semiconductor industry is not only in the favour of IIT/NITs everyone who so ever have talent to crack the problems, interest in VLSI and Semiconductor area can get a job in Semiconductor and VLSI industry. There are a number of startup companies in this domain which are providing good chances to real talent. Some of them are Masamb electronics systems, RF silicon, Silicon Mentor; Pass Semiconductor, Zepto Chip, GDA technologies etc. Tags : Silicon Mentor Zepto Chip Silab tech Spontey GDA Technologies Author - Dinesh Chauhan (Design Engineer at Silicon Mentor)

Here, we are introducing a LP-TPG (i.e. Low Power Test Pattern Generator, using Low Frequency Shift Register). Also we’d designed a conventional TPG. Now we will use Braun Array Multiplier, using both Ripple carry adder as well as Kogge stone adder. Now in our design, we’ll use outputs of both the test pattern generators as an input to both kinds of multipliers. Our whole architecture has being designed and simulated using MODELSIM SE 6.5 & synthesised on XLINX ISE DESIGN SUITE 13.3. Till now, we are getting four simulation windows as shown below, according to our design model. Further we are trying to implement our whole design on another software QUARTUS II 13.1. So as to analysis that power consumption i.e. static power, dynamic power, on chip power, off chip power in case of LP-TPG will be less than conventional TPG. Author - Akash Kumar (Research Associate at Silicon Mentor) Simulation window – Conventional TPG is connected to Braun Array Multiplier, using Ripple carry adder. Simulation window – LP-TPG is connected to Braun Array Multiplier, using Ripple carry adder. Simulation window – Conventional TPG is connected to Braun Array Multiplier, using Kogge stone adder Simulation window – LP-TPG is connected to Braun Array Multiplier, using Kogge stone adder

It sounds crazy when you say there is a device called FPGA that might replace ASIC. Definitely it will be a great achievement for the electronics engineers if they can make a hardware which can be used for all the electronic devices. Field Programmable Gate Array (FPGA) specifies that it can be configured by costumer or designer after manufacturing. Hardware description languages (HDLs), such as VHDL and Verilog are used to implement the logic. FPGA FPGAs have mainly four elements viz. CLBs, Interconnects, BRAMs and IOBs which makes them programmable. Configurable Logic Blocks (CLBs) are the main weapons to make device programmable. CLBs are made up of LUTs, flip-flop and a 2:1 mux. FPGA Look UP Tables (LUTs) are made up of small BRAMs that can implement any logic function. Each of inputs is essentially an address for the BRAM so that it can define the output logic to the block. 2 inputs LUT can become any logic gate. LUTs are then connected to the DFF which are the memory elements used to store the output from LUT. A 2:1 MUX is used in case you want to bypass the DFF (D-Flip-flop). Each logic block can connect through the Interconnects to their corresponding block to implement the desired logic. IOBs are used as an interface to the outer world. Author - Dharmendra Kumar (Research Associate at Silicon Mentor)

From the inverter, let’s move to the NAND gate. Being one of the universal gates, NAND gate holds utmost importance in any logic design NAND gate in HSPICE Fig. Shown on the top is a circuit diagram of a NAND gate in CMOS logic. If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and Vss (ground), bringing the output low. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and Vdd (voltage source), bringing the output high. An advantage of CMOS over NMOS is that both low-to-high and high-to-low output transitions are fast since the pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full voltage between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise. Netlist *CMOS 2-INPUT NAND GATE vdd 1 0 5 v1 4 0 pulse(0 3.3 0 1ps 1ps 500ns 1000ns) v2 3 0 pulse(0 3.3 0 1ps 1ps 1000ns 2000ns) m1 2 4 1 1 pmos1 w=13u l=3u m2 2 3 1 1 pmos1 w=13u l=3u m3 2 4 5 0 nmos1 w=8u l=3u m4 5 3 0 0 nmos1 w=8u l=3u *NMOS Device .model nmos1 nmos (LEVEL=2, UO=150, VTO=1.4581, GAMMA=1.8658, PHI=0.7974, + KP=1.0354e-5, LAMBDA=0.02, XJ=0.2u, LD=0.2u, PB=0.9939, + NSUB=5e16, NSS=2e10, TOX=50n, TPG=+1) *PMOS Device .model pmos1 pmos (LEVEL=2, UO=316.67, VTO=-1.5488, GAMMA=1.8658, PHI=0.7974, + KP=2.1860e-5, LAMBDA=0.02, XJ=0.2u, LD=0.2u, PB=0.9939, + NSUB=5e16, NSS=2e10, TOX=50nm, TPG=+1) .trans 1ns 5400ns 0.1ns .probe .end Tags : NAND gate NMOS CMOS NMOS PMOS SPICE Training Author - Amresh Kumar Singh (Trainee Engineer at Silicon Mentor)